(a) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a wiring board for use in mounting a semiconductor element or the like, and a method of manufacturing the same.
Note that the “wiring board” is hereinafter also referred to as a “semiconductor package” or merely a “package” for the sake of convenience, because the wiring board plays the role of mounting a semiconductor element or the like thereon.
(b) Description of the Related Art
A semiconductor package such as a ball grid array (BGA), a land grid array (LGA) or a pin grid array (PGA) generally has a multilayer wiring structure. The multilayer wiring structure is obtained, for example, by build-up process sequentially repeating the formation of a conductive pattern (wiring layer), the formation of an insulating layer, and the formation of a via hole in the insulating layer, on both surfaces of a core board provided as a base material for the semiconductor package. Finally, the outermost wiring layer is coated with a protection film, and an opening is formed at a required position in the protection film while a portion of the conductive pattern is exposed as a pad portion. In the case of the BGA or the PGA, a ball, a pin or the like which functions as an external connection terminal is further bonded to the exposed pad portion.
A semiconductor package of this type has a semiconductor element such as an IC chip mounted on a surface thereof with a conductive material such as solder therebetween. The semiconductor package with the semiconductor element mounted thereon is then packaged on a packaging object such as a motherboard or a socket component with an external connection terminal (such as a ball or a pin) therebetween, the external connection terminal provided on the other surface of the semiconductor package. Namely, the semiconductor element is electrically connected to the motherboard or the like with the semiconductor package therebetween.
Meanwhile, as demands for miniaturization and multiple functions in electronic equipment or an electronic device grow recently, a semiconductor device for use in the electronic equipment or the electronic device has been smaller in size, higher in packaging density, and higher in pin count (higher in terminal count). With this demand, a semiconductor device, called a chip size package or a die size package, has been developed and come into practical use, which is designed to achieve miniaturization by bringing the shape of the semiconductor device as close to that of an individual semiconductor element (chip) as possible.
An example of technology related to the above-mentioned prior art is described in Japanese unexamined Patent Publication (JPP) (Kokai) 8-167629. This publication discloses a semiconductor device, which includes a sealing resin to seal a semiconductor substrate, a lead pattern transferred to the underside of the sealing resin, and a plurality of external electrodes formed on the underside of the lead pattern.
Of the prior art semiconductor packages as mentioned above, the chip size package (die size package) has attracted attention in the course of development of recent downsizing; however, such a chip size package may possibly be deficient in the number of terminals under restrictions on a chip (die) size and a terminal pitch.
Namely, the increase in integration density per chip leads to the increase in the number of inputs and outputs, and to a need for a larger number of external connection terminals. A semiconductor package having an active IC chip such as a microprocessor unit (MPU) mounted thereon, in particular, requires a significantly larger power supply current. For this reason, a larger number of external connection terminals are assigned to the power supply to the chip in the semiconductor package, which account for more than half of the total terminals of the package. Namely, only less than half terminals thus left are available as inputs and outputs for signals.
On the other hand, the miniaturization of the package leads to a limited number of external connection terminals which can be built in the package. Accordingly, under the current circumstances, the prior art chip (die) size package has difficulty in ensuring a sufficient number of external connection terminals.
Furthermore, the mounting of the semiconductor element such as an IC chip on the semiconductor package involves: connecting an electrode terminal of the chip to the pad portion exposed on the chip mounting surface of the package, by flip chip bonding, using a conductive material such as solder; filling an underfill resin into a gap between the package and the chip; and heat-curing and thus setting the resin. At the time of heat curing, a difference in the coefficient of thermal expansion between the resin and the board causes a shrinkage in the underfill resin, resulting in warpage in the package affected by the shrinkage.
To reduce such “warpage” resulting from a cure shrinkage in the underfill resin at the time of chip mounting, the package (wiring board) needs to be configured in a considerable thickness (i.e. in multiple layers). Also, such a package generally has a multilayer structure under restrictions on the width of a wiring pattern or a via contact (interlayer connection) and thus has disadvantage of impairing the thinning (miniaturization) of the overall package.